Chris Angove has extensive hands-on experience of and a good knowledge of RF design techniques covering frequencies from HF to millimetre wave. The architectures used for the VHF, UHF and SHF ranges have most usually been various microstrip forms (FR4, alumina and other low loss and mixed dielectrics). Other types have included co-planar strips, co-planar waveguide and buried track (stripline/triplate) types. He is also familiar with rectangular waveguide components designed to work in TE10 mode and circular TE11 mode. The millimetre wave work used rectangular waveguide components and beam waveguide structures (reflective and transmissive types).
He is familiar with both the obvious and the more subtle issues that are encountered frequently in RF engineering including:
high frequency skin depths
good grounding practice
screening and filtering (low and high frequency)
isolation and leakage, absorption
reflections, spurious oscillations
distortion (harmonics, intermodulation, P1db, IP3) and noise ( kTB, Shot)
S-parameters (including multi-port)
Smith Chart techniques
passive intermodulation products
high dielectric breakdown
unexpected mode generation
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Silicon bipolar technology has now been developing for around 40 years. It well understood and cheap. Discrete RF devices are now pushing well into gigahertz frequencies. These are some notes on discrete silicon RF transistors.
The emitter electrode structure is interdigital. The spacing of the emitter electrode fingers controls the high frequency performance of the device. Finer fingers give devices with more gain and lower noise figures but are more difficult to manufacture. The number of fingers controls the current and power handling capability of the device. Generally fewer fingers would be used in lower current devices, intended for battery operation and more fingers in the higher power stages. Typical pitches vary from 2mm to 10mm.
Many RF transistors are still used in packaged form instead of IC form. The reasons for this lie in the high frequency RF characteristics of the package. Small short bonding wires and pins can have undesirable and significant inductance and resistance at high frequencies. If these are replaced by wide tabs for example these will be much reduced. Some packages go one step further and provide two wide tabs for the emitter electrode thus reducing inductance and resistance even further for the common emitter configurations often used in RF circuits. The packaged form also gives more repeatable S parameter characterisation of the device which is necessary for any sort of reasonable matching, whether it be for maximum power, minimum noise figure or whatever.
VEBO Voltage between the emitter and base with the collector open circuit.
VCES Collector to emitter saturation voltage.
IC Collector current.
Tj Junction temperature.
Tstj Storage temperature.
The theory behind S or scattering parameters are discussed elsewhere (PDF). A grounded emitter transistor is a two port network and may therefore be represented by a 2 by 2 scattering matrix at a particular set of DC and RF operating conditions. Each S parameter is described in both magnitude and phase. The magnitude may be a linear value or converted to decibels (dB), referred to generically as logarithmic. For example, at VCE = 8 V, IC = 5 mA, f = 1 GHz and Z0 = 50 W:
S11 = 0.54(-152°)
S12 = -21.4 dB (33°)
S21 = 13.4 dB (85°)
S22 = 0.41(-63°).
Conventionally S parameters use port 1 for the input and port 2 for the output, but this is by no means universal. If this is the case, thenS11 is the input reflection coefficient S21 is the forward transfer coefficient S12 is the reverse transfer coefficient S22 is the output reflection coefficient
These parameters can be substituted into a host of equations that describe the behaviour of circuits or used with graphical aids such as Smith charts.
Transistor structures are designed according to the intended application of the device such as intermediate gain, oscillator applications or low noise.
Data sheets describing a device intended for a low noise amplifier (LNA) will generally include graphs of noise figure (NF) and associated gain (GA) against frequency for stated DC conditions of collector-emitter voltage (VCE), and collector current (IC). The NF may be further split into the 50 W case (NF50W) and the optimised case (NFopt).
At a given frequency, NFopt is the noise figure achieved from the device after its input has been 'matched' to the necessary complex source reflection coefficient for optimum NF. That is to say that a circuit has been connected to the input which means that the device 'sees' this complex reflection coefficient at its source a opposed to the more common system impedance such as 50 Ohm. The data sheet for a device intended for LNA applications usually includes a table of such values. Alternatively, the same information may be provided graphically on a Smith Chart with a set of constant noise figure circles. This NFopt 'matching' must be performed with caution. Any extra loss added at the front end will degrade the overall NF and this may be greater than the intended NF improvement. At lower frequencies there may be no noise figure improvement available at all by using this technique.
In a typical receiver application for example, an LNA would normally be at the front of a chain of stages, each of which provides some amplification (or loss) and a contribution to the overall noise figure dependent on these. The chain may include frequency conversion which we will need to think about later. Fris's formula, shown below, gives the overall noise figure for the whole cascade (FT), in terms of the gain and noise figure of each individual stage.
Fris's formula makes the following assumptions:
Fris's formula shows that it is the distribution of individual stage NF's and gains that determines the overall NF of the cascade and therefore of its small signal handling capability. For and individual stage, it is the gain associated with the NF that is important. This is why associated gain is usually given along with NF50W and NFopt.
GaAs has a higher electron mobility and a smaller resistivity than silicon and is therefore often more suitable as a semiconductor material for operation at higher frequencies, typically above about 4 GHz. GaAs FET amplification is due to voltage gain unlike in a bipolar device in which the mechanism is current gain. Matching is also usually less of an issue in GaAs FETs.
GaAs FET performance is largely determined by the gate length and width. The electrode geometry is such that the length and width are respectively the shorter and longer dimensions. The length sets the high frequency performance and needs to be as short as possible, consistent with adequate current density. The width determines the following:
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It is well worth doing several sets of S parameter measurements on several representative devices for use in the design and development work. Ideally some samples of devices should be taken from the production batch for this.
I have not done a study of the performance or value for money of any of the simulation packages available. I have used HP (now Agilent) ADS (Advanced Design System), AWR Microwave Office and Genesys. In my opinion ADS was the most powerful, but no doubt it is at a very powerful price as well. ADS includes a huge library of PDF manuals for everything imaginable and I am impressed by the detail with which everything is explained back to first principles with full references. However it takes a long time to search through all these and difficult to justify when your manager wants a result quickly. As well as RF/analog, it has a digital environment as well and seems to be well suited to cellular/mobile communications at system level as well.
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